SOI Matching Network Testchip

In the Module 2 research group a testchip design in 130nm SOI technology is finalized and delivered for production in July 2015!

The testchip includes matching networks and RF switches for different LTE bands. The SOI testchip can be assembled together with a CMOS transceiver SoC and power amplifiers in a system-in-package (SiP) enabling optimized transceiver frontend integration.


Fig. 1.  SOI testchip layout