First Testchip in Module 1 successfully taped
A first important milestone for the Module 1 research team was achieved in December 2014. After 6 months of hard work, Suchi und Aruna finalized the design and layout of a RF testchip in 65nm CMOS technology (a layout snapshot is shown in the Figure). The testchip includes two important RF building blocks. The first block is a fully reconfigurable balun low-noise amplifier (LNA) with continuously tunable gain and band. The second block is a “true” RMS power detector with a digital 8 bit digital interface based on a SAR ADC. With the power detector and the tunable LNA an automatic gain control (AGC) for the LNA can be implemented in the RF domain.