Author: sturm

Band-pass sampling receiver testchip

Our testchip of a multi-band band-pass sampling receiver for WLAN standard in 65nm CMOS arrived. The subsampling receiver is based on RF discrete time signal processing right after a tunable LNA circuit. The testchip contains two receive paths for  5

4th RF Workshop

The 4th RF workshop 2016 of the Radio Frequency Engineering Working Group of Austrian Research Association (ÖFG) was held at 17. and 18. October 2016 in the Holiday Inn / Congress Center Villach (CCV). Organized by the Josef Ressel Center

Program of RF workshop is online

The program of the 4th RF workshop of the Radio Frequency Engineering Working Group of Austrian Research Association (ÖFG) is now online: ⇒ 4th ARGE HFT Workshop Our Interact research team will provide 3 presentations during the 2-days workshop. Ajinkya

We are presenting at ESSCIRC 2016 conference

We are happy to show our work on tunable LNA’s at this years ESSCIRC conference in Lausanne.  Vijay will present the paper called “A Tunable Gain and Tunable Band Active Balun LNA for IEEE 802.11ac WLAN Receivers” during the “RF

Intel Fellow Zdravko Boos talks about “Challenges of the next Wireless Communication System – 5G”

In course of the “Forum Technik” lecture series at the Carinthia University of Applied Sciences Mr. Zdravko Boos gave a presentation about “Challenges of next Wireless Communication – 5G” on 12th May 2016.s Zdravko Boos is an Intel Fellow and

Interact intermediate review

On  28th of January 2016 the intermediate review meeting of our Josef Ressel Center “Interact” was organized at the Fachhochschule Kärtnen in Villach. An important milestone of a Josef Ressel Center is a mandatory review after 2 years. The center

Interact Workshop

For a detailed presentation and disussion of the latest research results,  the Interact team has invited for a workshop on 19.11.2015. Together with representatives from the project partner Intel Austria GmbH we had the chance to share our know-how and

SOI Matching Network Testchip

In the Module 2 research group a testchip design in 130nm SOI technology is finalized and delivered for production in July 2015! The testchip includes matching networks and RF switches for different LTE bands. The SOI testchip can be assembled

Matching Network in SiP Technology

A matching network for a RF transceiver front-end is realized in a substrate of a SiP technology. The matching network provides impedance transformation between a CMOS TX pre-amplifier to a power amplifier. A main building block of the matching network